In recent years, the capacity of a nonvolatile semiconductor storage device whose representative example is a flash memory has increased significantly and a product with a capacity of several hundreds of gigabytes has been released. The nonvolatile semiconductor storage device has a high commercial value as, particularly, a USB memory or a storage device for a mobile phone and is useful as a storage device for a portable music player since it has the advantages of a solid-state element memory, such as vibration resistance, high reliability, and low power consumption. Therefore, the nonvolatile semiconductor storage device has been mainly used as a storage device for a portable or mobile electronic apparatus for music and images.
In addition to the application of the storage device, a computer in which nonvolatility is given to a DRAM that is being currently used as the main memory of an information apparatus and which instantly starts up in use and consumes little power in a standby state, that is, a so-called “instant on computer” has been actively studied. In order to achieve the computer, a nonvolatile memory satisfying requirements (1) a switching speed of less than 50 ns and (2) the number of rewriting operations more than 1016, which are technical specifications required for the DRAM, is needed.
As the candidates of the next-generation nonvolatile semiconductor storage device, nonvolatile memory elements based on various kinds of principles, such as a ferroelectric memory (FeRAM), a magnetic memory (MRAM), and a phase-change memory (PRAM), have been studied and developed. However, the MRAM is looking very promising as the candidate satisfying the technical specifications for replacing the DRAM. Among the technical specifications, the number of rewriting operations (>1016) is considered on the basis of the number of accesses when an access operation is continuously performed at 30 ns for 10 years. In the case of a nonvolatile memory, since a refresh cycle is not needed, the number of accesses is not necessarily needed. The MRAM has already cleared a rewriting number function of 1012 or more, which is a trial level, and a high switching speed (<10 ns). Therefore, it is considered that the feasibility of the MRAM is more than that of other nonvolatile storage devices.
The first problem of the MRAM is a large cell area and high writing energy. An MRAM with a low capacity of about 4 Mbit that is currently commercially available is a current magnetic field rewriting type and has a very large cell area of 20 F2 to 30 F2 (F is the minimum feature size of a manufacturing process). Therefore, the low-capacity MRAM is not suitable for a technique replacing the DRAM. In order to solve these problems, there are two breakthroughs. One of the two breakthroughs is an MTJ (magnetic tunnel junction) using a MgO tunnel insulating film, which is a technique capable of easily obtaining a magnetic resistance of 200% or more (for example, see Non-patent Literature 1). The other breakthrough is a current induced magnetization reversal method (hereinafter, referred to as an STT), which is a technique capable of solving the problem of the reversal magnetic field being increased in a micro-cell which is a significant problem in the current magnetic field rewriting type, and reducing the writing energy by scaling. The current induced magnetization reversal type can ideally achieve a one-transistor-one-MTJ structure. Therefore, it is considered that the cell area of the MRAM is from 6 F2 to 8 F2, which is equal to that of the DRAM (for example, see Patent Literature 1 and Non-patent Literature 2).
The operation of the MRAM according to the related art will be described in brief with reference to FIG. 12. FIG. 12 is an enlarged cross-sectional view illustrating a portion of a storage device 10′ including a magnetic memory element 1′. However, the storage device 10′ shown in FIG. 12 has the same operation as that disclosed in Patent Literature 1.
The magnetic memory element 1′ includes a magnetic tunnel junction (MTJ) portion 13. The MTJ portion 13 is interposed between a lower electrode 14 and an upper electrode 12. The MTJ portion 13 has a structure in which a pinned layer 22 (first magnetic body), an insulating layer 21, and a storage layer 20 (second magnetic body) are sequentially stacked from the lower side (the side of the lower electrode 14) to the upper side (the side of the upper electrode 12). The pinned layer 22 and the storage layer 20 are perpendicular magnetization films. The lower electrode 14 is formed on a drain region 24 of a substrate 15 and a source region 25 is formed in the substrate 15 so as to be separated from the drain region 24. A gate line 16 is formed above the drain region 24 and the source region 25 so as to be insulated therefrom. The drain region 24, the source region 25, and the gate line 16 form a MOS-FET. In addition, a contact portion 17 and a word line 18 are sequentially stacked on the source region 25 and the word line 18 is connected to a control circuit (not shown). The upper electrode 12 is connected to a bit line 11 and the bit line 11 is connected to the control circuit (not shown). The bit line 11 and the word line 18 are insulated from each other by an interlayer insulating film 23.
Next, the principle of the operation of the magnetic memory element 1′ according to the related art will be described with reference to FIG. 13. FIG. 13 is an enlarged view illustrating the MTJ portion 13 shown in FIG. 12.
In the magnetic memory element 1′ configured as shown in FIG. 12, a resistance value varies depending on the magnetization direction of the storage layer 20 relative to the pinned layer 22 (TMR effect). Specifically, when the magnetization direction of the storage layer 20 is opposite to that of the pinned layer 22 as shown in FIG. 13(a), the insulating layer 21 is in a high resistance state. When the magnetization direction of the storage layer 20 is the same as that of the pinned layer 22 as shown in FIG. 13(b), the insulating layer 21 is in a low resistance state. The high resistance state corresponds to “0” and the low resistance state corresponds to “1” from the above-mentioned point. The magnetization state (data) of the storage layer 20 is read as a resistance value, which is the principle of a reading operation (see Non-patent Literature 1).
For a writing operation, as shown in FIG. 13(a), when a current 103 flows from the storage layer 20 to the pinned layer 22, the storage layer 20 is changed from the high resistance state to the low resistance state shown in FIG. 13(b). When a current flows in the opposite direction in the low resistance state, the storage layer 20 is changed from the low resistance state to the high resistance state shown in FIG. 13(a). This is the principle of the writing operation (see Non-patent Literature 2).
As described above, the storage device 10′ selects a MOS-FET using the magnetic memory element 1′, reads information stored in the magnetic memory element 1′, and writes information to the magnetic memory element 1′.